Forwarding data between multiple execution units in a super scalar design has been a problem which often limits the cycle time of the design. The result bus from each unit or the cache must be forwarded to other execution units, the GPR/FPR register files, the SPRs, other implementation dependent queues, and reservation stations or rename buffers. In current designs, the result busses are forwarded uniformly to all destinations (i.e., results are made available to all destinations in the same cycle). Uniform forwarding of data to all destinations results in heavy bus loading which becomes a critical performance degradation factor, either by limiting the cycle time or delaying the forwarding of data. This invention describes a non-uniform forwarding of data, as well as an instruction queuing and issuing mechanism to utilize all the execution units effectively.